-------------------------------------------------------------------------------
-- project_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity project_stub is
  port (
    fpga_0_RS232_PORT_RX_pin : in std_logic;
    fpga_0_RS232_PORT_TX_pin : out std_logic;
    fpga_0_LEDs_8Bit_GPIO_d_out_pin : out std_logic_vector(0 to 7);
    fpga_0_LED_7SEGMENT_GPIO_d_out_pin : out std_logic_vector(0 to 11);
    fpga_0_Push_Buttons_3Bit_GPIO_in_pin : in std_logic_vector(0 to 2);
    fpga_0_Switches_8Bit_GPIO_in_pin : in std_logic_vector(0 to 7);
    fpga_0_mem_signal_mux_0_A_Out_pin : out std_logic_vector(0 to 22);
    fpga_0_mem_signal_mux_0_DQ_pin : inout std_logic_vector(0 to 15);
    fpga_0_mem_signal_mux_0_CEN_M_O_pin : out std_logic;
    fpga_0_mem_signal_mux_0_OEN_pin : out std_logic;
    fpga_0_mem_signal_mux_0_WEN_pin : out std_logic;
    fpga_0_Micron_RAM_Mem_BEN_pin : out std_logic_vector(0 to 1);
    fpga_0_net_gnd_pin : out std_logic;
    fpga_0_net_gnd_1_pin : out std_logic;
    fpga_0_net_gnd_2_pin : out std_logic;
    fpga_0_mem_signal_mux_0_CEN_F_O_pin : out std_logic;
    fpga_0_INTEL_FLASH_Mem_RPN_pin : out std_logic;
    sys_clk_pin : in std_logic;
    sys_rst_pin : in std_logic
  );
end project_stub;

architecture STRUCTURE of project_stub is

  component project is
    port (
      fpga_0_RS232_PORT_RX_pin : in std_logic;
      fpga_0_RS232_PORT_TX_pin : out std_logic;
      fpga_0_LEDs_8Bit_GPIO_d_out_pin : out std_logic_vector(0 to 7);
      fpga_0_LED_7SEGMENT_GPIO_d_out_pin : out std_logic_vector(0 to 11);
      fpga_0_Push_Buttons_3Bit_GPIO_in_pin : in std_logic_vector(0 to 2);
      fpga_0_Switches_8Bit_GPIO_in_pin : in std_logic_vector(0 to 7);
      fpga_0_mem_signal_mux_0_A_Out_pin : out std_logic_vector(0 to 22);
      fpga_0_mem_signal_mux_0_DQ_pin : inout std_logic_vector(0 to 15);
      fpga_0_mem_signal_mux_0_CEN_M_O_pin : out std_logic;
      fpga_0_mem_signal_mux_0_OEN_pin : out std_logic;
      fpga_0_mem_signal_mux_0_WEN_pin : out std_logic;
      fpga_0_Micron_RAM_Mem_BEN_pin : out std_logic_vector(0 to 1);
      fpga_0_net_gnd_pin : out std_logic;
      fpga_0_net_gnd_1_pin : out std_logic;
      fpga_0_net_gnd_2_pin : out std_logic;
      fpga_0_mem_signal_mux_0_CEN_F_O_pin : out std_logic;
      fpga_0_INTEL_FLASH_Mem_RPN_pin : out std_logic;
      sys_clk_pin : in std_logic;
      sys_rst_pin : in std_logic
    );
  end component;

begin

  project_i : project
    port map (
      fpga_0_RS232_PORT_RX_pin => fpga_0_RS232_PORT_RX_pin,
      fpga_0_RS232_PORT_TX_pin => fpga_0_RS232_PORT_TX_pin,
      fpga_0_LEDs_8Bit_GPIO_d_out_pin => fpga_0_LEDs_8Bit_GPIO_d_out_pin,
      fpga_0_LED_7SEGMENT_GPIO_d_out_pin => fpga_0_LED_7SEGMENT_GPIO_d_out_pin,
      fpga_0_Push_Buttons_3Bit_GPIO_in_pin => fpga_0_Push_Buttons_3Bit_GPIO_in_pin,
      fpga_0_Switches_8Bit_GPIO_in_pin => fpga_0_Switches_8Bit_GPIO_in_pin,
      fpga_0_mem_signal_mux_0_A_Out_pin => fpga_0_mem_signal_mux_0_A_Out_pin,
      fpga_0_mem_signal_mux_0_DQ_pin => fpga_0_mem_signal_mux_0_DQ_pin,
      fpga_0_mem_signal_mux_0_CEN_M_O_pin => fpga_0_mem_signal_mux_0_CEN_M_O_pin,
      fpga_0_mem_signal_mux_0_OEN_pin => fpga_0_mem_signal_mux_0_OEN_pin,
      fpga_0_mem_signal_mux_0_WEN_pin => fpga_0_mem_signal_mux_0_WEN_pin,
      fpga_0_Micron_RAM_Mem_BEN_pin => fpga_0_Micron_RAM_Mem_BEN_pin,
      fpga_0_net_gnd_pin => fpga_0_net_gnd_pin,
      fpga_0_net_gnd_1_pin => fpga_0_net_gnd_1_pin,
      fpga_0_net_gnd_2_pin => fpga_0_net_gnd_2_pin,
      fpga_0_mem_signal_mux_0_CEN_F_O_pin => fpga_0_mem_signal_mux_0_CEN_F_O_pin,
      fpga_0_INTEL_FLASH_Mem_RPN_pin => fpga_0_INTEL_FLASH_Mem_RPN_pin,
      sys_clk_pin => sys_clk_pin,
      sys_rst_pin => sys_rst_pin
    );

end architecture STRUCTURE;

